The present invention relates generally to circuit synthesis and, specifically, to a method and apparatus for allowing a user to easily enter, change, and evaluate timing constraints for a circuit design.
Debugging the timing of a circuit design is an extremely complex design task. Various conventional software products assist a human designer in performing circuit design and analysis. For example, Design Compiler.TM. sold by Synopsys, Inc. of Mountain View, Calif. includes a timing verifier that assists in the design process. The primary user-entered command used to generate timing information in Design Compiler.TM. is "report.sub.-- timing." The portion of the manual page for the report.sub.-- timing command in Design Compiler version 1998.02, available from Synopsys, Inc. of Mountain View, Calif. is hereby incorporated by reference. When the Design Compiler software executes, it accepts a command from a user, such as "report.sub.-- timing." After the user enters this command, the software generates a tabular report that indicates the delay through the longest path in each clock domain. This report is static and cannot be altered by the user.
If the user wants to modify the behavior of report.sub.-- timing, the user must enter yet another command: the "group.sub.-- path" command. The portion of the manual page for the group.sub.-- path command in Design Compiler version 1998.02, available from Synopsys, Inc. of Mountain View, Calif. is hereby incorporated by reference. The "group.sub.-- path" command allows the user to specify a custom group of signal paths so that report.sub.-- timing shows the worst path in each custom path group. Although this approach is very general, it requires the user to carefully determine valid path start and end points for each path. Path start points are input ports to the circuit, and clock pins on registers. Path end points are output ports of the circuit, and data pins on registers. The user must either use commands to specifically identify all of the ports and/or registers, or must know the names of specific ports and/or registers. Alternatively, the user must specify the start and end points of a path when using the report.sub.-- timing command. To see the delay for multiple paths simultaneously the user must specify how many paths to report.
Another approach to debugging timing is described in co-pending U.S. application Ser. No. 08/266,147, entitled "Architecture and Methods for a Hardware Description Language Source Level Analysis and Debugging System" of Craven et al., which is hereby incorporated by reference. This application describes Path Browser software. The Path Browser software requires the user to identify the appropriate endpoint for the path. Then a single path is displayed, but individual cell delay numbers are not shown with the cells.